Vlad B Bril

US Patent:

6542150, Apr 1, 2003

Filed:

Jun 28, 1996

Appl. No.:

08/671873

Inventors:

Sridhar Kotha - Fremont CA
Vlad Bril - Campbell CA
Alexander J. Eglit - Half Moon Bay CA

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

G09G 500

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

7209133, Apr 24, 2007

Filed:

Feb 7, 2003

Appl. No.:

10/359734

Inventors:

Alexander J. Eglit - Half Moon Bay CA, US
Sridhar Kotha - Fremont CA, US
Vlad Bril - Campbell CA, US

Assignee:

NVIDIA International, Inc. - St. Michael

International Classification:

G09G 5/00
G09G 3/18

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

7623126, Nov 24, 2009

Filed:

Jun 17, 2003

Appl. No.:

10/463840

Inventors:

Alexander J. Eglit - Half Moon Bay CA, US
Sridhar Kotha - Fremont CA, US
Vlad Bril - Campbell CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/00
G09G 3/18

US Classification:

345213, 345 53, 345208

Abstract:

A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.

US Patent:

20090128452, May 21, 2009

Filed:

Jan 23, 2009

Appl. No.:

12/359047

Inventors:

Vlad Bril - Campbell CA, US
Kris Narayan - Pleasanton CA, US

International Classification:

G09G 3/20

US Classification:

345 55

Abstract:

A personal computer (PC) monitor system is disclosed in accordance with an embodiment of the present invention to include a display unit and a base coupled the display unit for use by a user. The base includes a control module responsive to input television (TV) signals for processing the same to generate output TV signals, the control module further responsive to input PC data for processing the same to generate output PC data, the control module fixer responsive to input network application data for processing the same to generate output network application data, the control module further responsive to pointer data and low-resolution data, wherein the control module overlays the output network application data, the pointer data, and the low-resolution data to generate a first overlaid output data. The control module transfers the first overlaid output data, the output TV signals, and the output PC data to the display unit for viewing by a user.

US Patent:

60783192, Jun 20, 2000

Filed:

Apr 17, 1995

Appl. No.:

8/423251

Inventors:

Vlad Bril - Campbell CA
Sagar Waman Kenkare - Fremont CA
Thomas Shieh-Luen Ho - Santa Clara CA
Edmund Christian Strauss - San Jose CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 500

US Classification:

345211

Abstract:

An integrated circuit such as a video controller may be provided with core logic circuitry using CMOS technology which may be operated at different supply voltages such as 3. 3 or 5 Volts. At lower supply voltages, the CMOS circuitry may run slower. For a video controller, certain higher resolution, pixel depths, and refresh rates may require high speed operation of the video controller. A monitoring circuit monitors the video mode, pixel resolution, pixel depth, and refresh rate and determines which supply voltage may be used to operate the video controller at such levels. An output signal from the monitoring circuit may be used by a switching circuit to supply an appropriate supply voltage to the integrated circuit. At lower performance levels, the integrated circuit may be operated at lower voltages to conserve power.

US Patent:

60056304, Dec 21, 1999

Filed:

Feb 4, 1999

Appl. No.:

9/244001

Inventors:

Vlad Bril - Campbell CA

Assignee:

TeleCruz Technology, Inc. - San Jose CA

International Classification:

H04N 201

US Classification:

348446

Abstract:

A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i. e. , only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.

US Patent:

59460512, Aug 31, 1999

Filed:

Jun 2, 1997

Appl. No.:

8/867203

Inventors:

Vlad Bril - Campbell CA

Assignee:

TeleCruz Technology, Inc. - San Jose CA

International Classification:

H04N 5445

US Classification:

348553

Abstract:

A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.

US Patent:

56110413, Mar 11, 1997

Filed:

Dec 19, 1994

Appl. No.:

8/359315

Inventors:

Vlad Bril - Campbell CA
Alexander Eglit - San Carlos CA
Sagar W. Kenkare - Fremont CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1200

US Classification:

395507

Abstract:

A memory controller, particularly for use in a video controller, is provided which reduces the effect of page misses during memory access. A video port FIFO is provided for buffering data from a video port to a display memory. A CRT FIFO is provided for buffering data from a display memory to a display. If, during a video port FIFO cycle, a page miss is encountered, the video port FIFO cycle is terminated and processing passes to a CRT FIFO CYCLE. If a page miss is encountered during a CRT FIFO cycle, the subsequent video port FIFO cycle will shortened by a number of memory cycles to compensate for the additional memory cycles required by the page miss. Additional data accumulated in the video port FIFO may be transferred to the display memory during a retrace interval. In this manner, memory bandwidth is optimized by removing a non-aligned page miss as the worst case of memory bandwidth utilization.

Address:

232 Darryl Dr, Campbell, CA 95008

Phone:

4083741481

VIN:

1G4HC5EM4BU136559

Make:

BUICK

Model:

LUCERNE

Year:

2011