Waldemar Peter Horwat

US Patent:

60212756, Feb 1, 2000

Filed:

Aug 5, 1996

Appl. No.:

8/692357

Inventors:

Waldemar Horwat - Sunnyvale CA

Assignee:

General Magic, Inc. - Sunnyvale CA

International Classification:

G06F 1210

US Classification:

395707

Abstract:

Endian format affects the representation of both literal data and pointer data whether represented in a global data specification (i. e. , in a data section) or as immediate operand values in-line with Intercode instructions. The present invention provides for endian-independent representation of literal data, pointer data, literal operands and pointer operands. For literal data represented in a data section, an associated data translation script provides an Intercode translator with translation instructions for transforming byte ordering within the data section on a unit-of-storage by unit-of-storage basis (if required for the particular target processor). In this way, literal data of arbitrary structure can be specified independent of endian format. For pointer data represented in the data section, the associated data translation script provides the Intercode translator with relocation expressions for transforming pointer data values to effective memory addresses. Relocation expressions compute a linear combination of relterms, wherein relterms include constants, data section addresses, function gate addresses, and translation time constants.

US Patent:

52127788, May 18, 1993

Filed:

May 27, 1988

Appl. No.:

7/200003

Inventors:

William J. Dally - Framingham MA
Andrew A. Chien - Urbana IL
Waldemar P. Horwat - Hoffman Estates IL
Stuart Fiske - Montreal, CA

Assignee:

Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 1516
G06F 932
G06F 1206
G06F 1300

US Classification:

395400

Abstract:

A message-driven concurrent computer system stores incoming messages in a row buffer and then in a queue in main memory. A translator cache is also located in main memory, and output from the cache is through a set of comparators. Both the queue and cache are addressed in a wraparound fashion by hardware. An instruction buffer holds an entire row of instructions from memory. Translate, suspend and send instructions are available to the user. Tags provide for synchronization when objects are retrieved from remote processors and identify addresses as being physical addresses of a local processor or a node address of a remote processor.