William H Atwell

US Patent:

6477104, Nov 5, 2002

Filed:

Apr 5, 1999

Appl. No.:

09/286178

Inventors:

William Daune Atwell - Spicewood TX
Michael L. Longwell - Austin TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX
Motorola Inc. - Schaumburg IL

International Classification:

G11C 700

US Classification:

365226, 365200

Abstract:

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provided the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( 41 ).

US Patent:

6646941, Nov 11, 2003

Filed:

Apr 30, 1999

Appl. No.:

09/303223

Inventors:

William Daune Atwell - Spicewood TX
Michael L. Longwell - Austin TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX

International Classification:

G11C 700

US Classification:

365222, 36523006

Abstract:

An apparatus for operating a dynamic memory ( ) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

US Patent:

62494759, Jun 19, 2001

Filed:

Apr 5, 1999

Appl. No.:

9/286186

Inventors:

William Daune Atwell - Spicewood TX
Michael L. Longwell - Austin TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX

International Classification:

G11C 800

US Classification:

36523003

Abstract:

A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c").

US Patent:

62726706, Aug 7, 2001

Filed:

Apr 5, 1999

Appl. No.:

9/286188

Inventors:

Jeffrey Van Myers - Driftwood TX
Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX

Assignee:

Madrone Solutions, Inc. - Austin TX

International Classification:

G06F 1750

US Classification:

716 17

Abstract:

In one embodiment, a plurality of atomic charge pumps (52, 54, 56) are connected together in series to form a distributed charge source (24). The atomic charge pumps (52, 54, 56) are operated sequentially over time to reduce supply signal noise. In addition, the distibuted charge source (24) is compatible with low power applications because each atomic charge pump (52, 54, 56) can be independently powered down if it is not required.

Author:

William D. Atwell

ISBN #:

0201634228