Michael L. Longwell - Austin TX William Daune Atwell - Spicewood TX Jeffrey Van Myers - Driftwood TX
Assignee:
Madrone Solutions, Inc - Spicewood TX
International Classification:
G11C 700
US Classification:
365222, 36523003, 365149
Abstract:
A method for operating a dynamic memory ( ) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).
William Daune Atwell - Spicewood TX Michael L. Longwell - Austin TX Jeffrey Van Myers - Driftwood TX
Assignee:
Madrone Solutions, Inc. - Austin TX Motorola Inc. - Schaumburg IL
International Classification:
G11C 700
US Classification:
365226, 365200
Abstract:
A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provided the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( 41 ).
Michael L. Longwell - Austin TX William Daune Atwell - Spicewood TX Jeffrey Van Myers - Driftwood TX
Assignee:
Madrone Solutions, Inc. - Austin TX Motorola, Inc. - Shaumburg IL
International Classification:
G11C 700
US Classification:
365226, 365200, 36523003
Abstract:
A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provide the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( ). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( รข).
Method For Apparatus For Tracking Errors In A Memory System
A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.
Apparatus For Operating An Integrated Circuit Having A Sleep Mode
William Daune Atwell - Spicewood TX Michael L. Longwell - Austin TX Jeffrey Van Myers - Driftwood TX
Assignee:
Madrone Solutions, Inc. - Austin TX
International Classification:
G11C 700
US Classification:
365222, 36523006
Abstract:
An apparatus for operating a dynamic memory ( ) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).
Method And Apparatus For Error Detection And Correction
Michael L. Longwell - Austin TX, US William Daune Atwell - Spicewood TX, US Jeffrey Van Myers - Driftwood TX, US
Assignee:
Madrone Solutions, Inc. - Spicewood TX
International Classification:
G06F 11/00 G11C 29/00
US Classification:
714800, 714763
Abstract:
A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.
Method And Apparatus For Error Detection And Correction
Michael L. Longwell - Austin TX, US William Daune Atwell - Spicewood TX, US Jeffrey Van Myers - Driftwood TX, US
Assignee:
Madrone Solutions, Inc. - Spicewood TX
International Classification:
G06F 11/00 G11C 29/00
US Classification:
714800, 714763
Abstract:
A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.
Method For Apparatus For Tracking Errors In A Memory System
Michael Longwell - Austin TX, US William Atwell - Spicewood TX, US Jeffrey Myers - Driftwood TX, US
International Classification:
H02H003/05
US Classification:
714/042000
Abstract:
A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of said detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.
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