William D Atwell

US Patent:

6385113, May 7, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/303284

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc - Spicewood TX

International Classification:

G11C 700

US Classification:

365222, 36523003, 365149

Abstract:

A method for operating a dynamic memory ( ) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

US Patent:

6552947, Apr 22, 2003

Filed:

Apr 5, 1999

Appl. No.:

09/286196

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX
Motorola, Inc. - Shaumburg IL

International Classification:

G11C 700

US Classification:

365226, 365200, 36523003

Abstract:

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provide the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( ). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( â).

US Patent:

6560725, May 6, 2003

Filed:

Jun 18, 1999

Appl. No.:

09/335992

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX

International Classification:

G06F 1100

US Classification:

714 54, 714 48, 714704, 714718, 714763, 714764, 711105, 711106

Abstract:

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

US Patent:

7134069, Nov 7, 2006

Filed:

Jun 16, 1999

Appl. No.:

09/334238

Inventors:

Michael L. Longwell - Austin TX, US
William Daune Atwell - Spicewood TX, US
Jeffrey Van Myers - Driftwood TX, US

Assignee:

Madrone Solutions, Inc. - Spicewood TX

International Classification:

G06F 11/00
G11C 29/00

US Classification:

714800, 714763

Abstract:

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

US Patent:

7644348, Jan 5, 2010

Filed:

Sep 11, 2006

Appl. No.:

11/518824

Inventors:

Michael L. Longwell - Austin TX, US
William Daune Atwell - Spicewood TX, US
Jeffrey Van Myers - Driftwood TX, US

Assignee:

Madrone Solutions, Inc. - Spicewood TX

International Classification:

G06F 11/00
G11C 29/00

US Classification:

714800, 714763

Abstract:

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

US Patent:

20030135794, Jul 17, 2003

Filed:

Mar 14, 2003

Appl. No.:

10/389666

Inventors:

Michael Longwell - Austin TX, US
William Atwell - Spicewood TX, US
Jeffrey Myers - Driftwood TX, US

International Classification:

H02H003/05

US Classification:

714/042000

Abstract:

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of said detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

US Patent:

20100083065, Apr 1, 2010

Filed:

Dec 1, 2009

Appl. No.:

12/592645

Inventors:

Michael L. Longwell - Austin TX, US
William Daune Atwell - Spicewood TX, US
Jeffrey Van Myers - Driftwood TX, US

International Classification:

H03M 13/09
G06F 11/07
G06F 11/10

US Classification:

714746, 714805, 714E11023, 714E11034

Abstract:

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

US Patent:

53697529, Nov 29, 1994

Filed:

Jun 1, 1992

Appl. No.:

7/891241

Inventors:

Grady L. Giles - Austin TX
William D. Atwell - Austin TX
Jesse R. Wilson - Austin TX
Richard B. Reis - Garland TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1202

US Classification:

395425

Abstract:

A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.

Author:

William D. Atwell

ISBN #:

0201634228