William T Hatley

US Patent:

7489706, Feb 10, 2009

Filed:

Jun 28, 2004

Appl. No.:

10/879988

Inventors:

William T. Hatley - San Jose CA, US
Roy Liang Chua - Sunnyvale CA, US

Assignee:

Spirent Communications, Inc. - Calabasas CA

International Classification:

H04J 3/06

US Classification:

370469, 370503

Abstract:

Timestamp information can be placed in a frame that includes a first portion processable at a selected layer of a protocol stack and a second portion processable at a lower protocol layer of the protocol stack subsequently to the processing of the first portion, wherein the first portion is contained within the second portion and wherein a numerically computed error detection code for the second portion is computed during processing of the second portion. A timestamp signature having a timestamp subfield of initialized data and a corrector subfield of initialized data is embedded in the first portion during processing thereof at the selected protocol layer. A numerical constant functionally equivalent to the numerically computed error detection code is determinable from the initialized data in the timestamp subfield and the corrector subfield. The data in said timestamp subfield is modified with timestamp information subsequently to processing of the second portion at the lower protocol layer. The data in the corrector subfield is then modified such that the numerical constant as determinable from the modified data in the timestamp subfield and the corrector subfield remains unchanged, whereby the numerically computed error detection code computed at the lower protocol layer remains valid.

US Patent:

7594159, Sep 22, 2009

Filed:

Oct 26, 2004

Appl. No.:

10/974214

Inventors:

Craig Glenn Fujikami - Honolulu HI, US
William Thomas Hatley - San Jose CA, US
Jocelyn Tamie Kunimitsu - Honolulu HI, US
Jon Kanji Otaguro - Honolulu HI, US
Carl Masami Uyehara - Kaneohe HI, US

Assignee:

Spirent Communications Inc. - Calabasas CA

International Classification:

H03M 13/00
H03M 13/51

US Classification:

714776, 714807

Abstract:

Information is added to an encapsulated payload in a data field of a frame subsequently to placing a checksum into a checksum field of a header encapsulating the payload, wherein the checksum has been determined from byte values of the header and the payload, yet having the checksum remaining detectable as valid upon interpretation of the header and the payload. A signature field that contains the information is inserted into the data field. The signature field has a checksum cheater subfield. A one's complement of a checksum determined from byte values of the information is then placed into the checksum cheater subfield. Accordingly, the checksum in the checksum field of the header remains valid.

US Patent:

7869381, Jan 11, 2011

Filed:

Sep 21, 2009

Appl. No.:

12/563471

Inventors:

William T. Hatley - San Jose CA, US
Thomas R. McBeath - Calabasas CA, US

Assignee:

Spirent Communications, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

US Patent:

7872987, Jan 18, 2011

Filed:

Sep 21, 2009

Appl. No.:

12/563431

Inventors:

William T. Hatley - San Jose CA, US
Thomas R. McBeath - Calabasas CA, US

Assignee:

Spirent Communications, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

US Patent:

7872988, Jan 18, 2011

Filed:

Sep 21, 2009

Appl. No.:

12/563453

Inventors:

William T. Hatley - San Jose CA, US
Thomas R. McBeath - Calabasas CA, US

Assignee:

Spirent Communications, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

US Patent:

7933220, Apr 26, 2011

Filed:

Sep 21, 2009

Appl. No.:

12/563399

Inventors:

William T. Hatley - San Jose CA, US
Thomas R. McBeath - Calabasas CA, US

Assignee:

Spirent Communications, Inc. - Sunnyvale CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

US Patent:

8102776, Jan 24, 2012

Filed:

Sep 5, 2007

Appl. No.:

11/899358

Inventors:

Craig Fujikami - Honolulu HI, US
William T. Hatley - San Jose CA, US
Jocelyn Kunimitsu - Honolulu HI, US

Assignee:

Spirent Communications, Inc. - Sunnyvale CA

International Classification:

H04L 12/26
H04L 12/56

US Classification:

370241, 370394

Abstract:

Embodiments of the invention relate to generating simulated network traffic. In some embodiments, simulated network traffic may be generated using a specification of a sequence of frames to be transmitted from the network testing device. The specification may specify at least two frames including a first frame and a second frame. The specification may further specify a first interframe gap associated with the first frame and a second interframe gap, having a different length from the first interframe gap, associated with the second frame. In some embodiments, the specification may specify an interframe gap for each frame in the sequence of frames. This information may be used to determine the relative transmit time of each frame to be transmitted. Because the specification identifies an interframe gap for each frame in the sequence, in some embodiments, multi-frame burst network traffic may be generated.

US Patent:

8310952, Nov 13, 2012

Filed:

Mar 28, 2011

Appl. No.:

13/073586

Inventors:

William T. Hatley - San Jose CA, US
Thomas R. McBeath - Calabasas CA, US

Assignee:

Spirent Communications, Inc. - Calabasas CA

International Classification:

H04L 12/26

US Classification:

370252

Abstract:

Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure.

Address:

1116 Casaba Crk Ct, San Jose, CA 95120

VIN:

YV1MH682372310364

Make:

VOLVO

Model:

S40

Year:

2007