William Troy Orso

US Patent:

61604100, Dec 12, 2000

Filed:

Mar 24, 1998

Appl. No.:

9/046757

Inventors:

William R. Orso - Milpitas CA
Khushrav S. Chhor - Fremont CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G01R 104

US Classification:

324757

Abstract:

An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

US Patent:

60186860, Jan 25, 2000

Filed:

Oct 31, 1997

Appl. No.:

8/962519

Inventors:

William R. Orso - Milpitas CA
Craig M. Nishizaki - San Mateo CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1900
G06F 766

US Classification:

700121

Abstract:

An integrated circuit, a programming mechanism and a method are provided for programming manufacturing information upon non-volatile storage devices of the integrated circuit. The storage devices may be programmed after manufacture and prior to assembling the integrated circuit within a semiconductor package. Thereafter, the packaged circuit can be tested to determine where, how and when the integrated circuit was manufactured from among possibly numerous die within a wafer and wafer lot. The storage locations which receive manufacturing indicia are addressed in an address location entirely separate from the addresses which receive data during normal operation of the integrated circuit. Accordingly, manufacturing information is accessible by the manufacturer, and the customer is preferably made unaware of the address space employing those storage locations.

US Patent:

60576960, May 2, 2000

Filed:

Mar 24, 1998

Appl. No.:

9/046962

Inventors:

William R. Orso - Milpitas CA
Khushrav S. Chhor - Fremont CA
Joseph D. Caliston - Bacolod, PH

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G01R 3126

US Classification:

324758

Abstract:

An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment.

US Patent:

62091107, Mar 27, 2001

Filed:

Mar 30, 1998

Appl. No.:

9/050242

Inventors:

Khushrav S. Chhor - Fremont CA
William R. Orso - Milpitas CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C29/00

US Classification:

714718

Abstract:

An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.