Yasuharu Sato

US Patent:

6377513, Apr 23, 2002

Filed:

Mar 6, 2001

Appl. No.:

09/763627

Inventors:

Masahiro Niimi - Kasugai, JP
Yasuharu Sato - San Jose CA
Tadao Aikawa - Kawasaki, JP
Hitoshi Ikeda - Kawasaki, JP
Hiroyuki Kobayashi - San Jose CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G11C 800

US Classification:

365233

Abstract:

A semiconductor memory device that performs a flash write operation without increasing the circuit area. Column selection lines CL -CL extend parallel to word lines at locations corresponding to where column gates are formed. During a flash write mode, the subcolumn decoder simultaneously selects the column selection lines. This writes cell information to every memory cell connected to the selected word line.

US Patent:

6498522, Dec 24, 2002

Filed:

Apr 12, 2001

Appl. No.:

09/833045

Inventors:

Hitoshi Ikeda - Kawasaki, JP
Shinya Fujioka - Kawasaki, JP
Yasuharu Sato - San Jose CA
Yasurou Matsuzaki - Kawasaki, JP

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03L 700

US Classification:

327141, 327 99, 327407, 365233

Abstract:

The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.