Zhonghua H Wu from 2030 Castillejo Way, Fremont, CA 94539, age 58, Phone: 5104568494

Three-Dimensional Coiling Via Structure For Impedance Tuning Of Impedance Discontinuity
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US Patent:

20120112868, May 10, 2012
Filed:

May 4, 2011
Appl. No.:

13/100687
Inventors:

Zhonghua (Ken) Wu - Fremont CA, US
Reza Sharifi - Irvine CA, US
Assignee:

Broadcom Corporation - Irvine CA
International Classification:

H01F 5/04
H05K 3/00
US Classification:

336200, 29829
Abstract:

Methods, systems, and apparatuses are provided for three-dimensional coiling via structures. A substrate includes a plurality of insulating layers, a plurality of trace layers interleaved with the insulating layers, and a three-dimensional coiling via. The three-dimensional coiling via includes a plurality of electrically conductive traces and a plurality of electrically conductive vias through the insulating layers. The electrically conductive traces are present in at least two of the traces layers and are coupled together by the electrically conductive vias. The electrically conductive traces are arranged to form at least one partial turn around an axis through the substrate.

Signal Routing In Integrated Circuit Packaging
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US Patent:

20220254711, Aug 11, 2022
Filed:

Mar 1, 2022
Appl. No.:

17/684218
Inventors:

- Mountain View CA, US
Zhonghua Wu - Fremont CA, US
International Classification:

H01L 23/50
H01L 23/498
H01L 23/528
Abstract:

In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.

Signal Routing In Integrated Circuit Packaging
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US Patent:

20200395290, Dec 17, 2020
Filed:

Jun 24, 2020
Appl. No.:

16/910244
Inventors:

- Mountain View CA, US
Zhonghua Wu - Fremont CA, US
International Classification:

H01L 23/50
H01L 23/498
H01L 23/528
Abstract:

In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.

Signal Routing In Integrated Circuit Packaging
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US Patent:

20190348360, Nov 14, 2019
Filed:

Oct 2, 2018
Appl. No.:

16/474687
Inventors:

- Mountain View CA, US
Zhonghua WU - Mountain View CA, US
International Classification:

H01L 23/50
H01L 23/498
H01L 23/528
Abstract:

In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.

Systems And Methods For High-Speed, Low-Profile Memory Packages And Pinout Designs
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US Patent:

20170162546, Jun 8, 2017
Filed:

Feb 17, 2017
Appl. No.:

15/435719
Inventors:

- Cupertino CA, US
Evan R. Boyle - Cupertino CA, US
Zhiping Yang - Cupertino CA, US
Zhonghua Wu - Cupertino CA, US
International Classification:

H01L 25/065
H01L 23/498
H01L 25/00
Abstract:

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Systems And Methods For High-Speed, Low-Profile Memory Packages And Pinout Designs
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US Patent:

20170005056, Jan 5, 2017
Filed:

Sep 15, 2016
Appl. No.:

15/266752
Inventors:

- Cupertino CA, US
Evan R. Boyle - Cupertino CA, US
Zhiping Yang - Cupertino CA, US
Zhonghua Wu - Cupertino CA, US
International Classification:

H01L 23/00
H01L 25/065
Abstract:

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Electrical Connector
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US Patent:

20160308318, Oct 20, 2016
Filed:

Dec 5, 2014
Appl. No.:

15/103033
Inventors:

- Mountain View CA, US
Adam Rodriguez - San Francisco CA, US
Zhonghua Wu - Fremont CA, US
International Classification:

H01R 27/00
H01R 13/02
H01R 13/03
H01R 24/62
Abstract:

An electrical connector may include a cord comprising wires and a plug extending from the cord. The plug may include a first top row of contacts included in a top portion of the plug and a first bottom row of contacts included in a bottom portion of the plug. The first top row of contacts may be coupled to the plurality of wires and include a first top differential signaling pair configured to carry signals according to a first communication protocol, and a second top differential signaling pair configured to carry signals according to a second communication protocol. The first bottom row of contacts may be coupled to the first top row of contacts and arranged to maintain a same arrangement of contacts and electrical paths the first top row of contacts to the plurality of wires when the plug is rotated one hundred and eighty degrees.

Systems And Methods For High-Speed, Low-Profile Memory Packages And Pinout Designs
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US Patent:

20150325560, Nov 12, 2015
Filed:

Jul 17, 2015
Appl. No.:

14/802750
Inventors:

- Cupertino CA, US
Evan R. Boyle - Cupertino CA, US
Zhiping Yang - Cupertino CA, US
Zhonghua Wu - Cupertino CA, US
International Classification:

H01L 25/18
H01L 23/00
H01L 23/60
H01L 21/56
H01L 21/48
H01L 25/065
H01L 25/00
H01L 23/498
H01L 23/528
Abstract:

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.