Ali B Icel

US Patent:

7531403, May 12, 2009

Filed:

Oct 2, 2006

Appl. No.:

11/538001

Inventors:

Ali Icel - Cupertino CA, US
Qiang Chen - Sunnyvale CA, US
Mario M. Pelella - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438201, 438199, 257E21545

Abstract:

SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

US Patent:

7844927, Nov 30, 2010

Filed:

Jan 19, 2007

Appl. No.:

11/655534

Inventors:

Zhi-Yuan Wu - Union City CA, US
Ali Icel - Cupertino CA, US
Judy X. An - San Jose CA, US
Ciby T. Thuruthiyil - Fremont CA, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6, 703 14

Abstract:

According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation.

US Patent:

7986008, Jul 26, 2011

Filed:

Mar 27, 2009

Appl. No.:

12/413185

Inventors:

Ali Icel - Cupertino CA, US
Qiang Chen - Sunnyvale CA, US
Mario M. Pelella - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 27/12

US Classification:

257351, 438153

Abstract:

SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

US Patent:

52486249, Sep 28, 1993

Filed:

Aug 23, 1991

Appl. No.:

7/749076

Inventors:

Ali B. Icel - Sunnyvale CA
Omer L. Akkan - San Jose CA

Assignee:

Exar Corporation - San Jose CA

International Classification:

H01L 21331
H01L 21336

US Classification:

437 31

Abstract:

A method and apparatus for an improved isolated vertical PNP in a complementary BICMOS process with EEPROM memory is provided. The isolated vertical PNP transistor is formed on a P-substrate with a P-epitaxial (EPI) layer. The collector of the vertical PNP transistor is isolated with an N- buried layer formed in the P substrate and an N+ buried layer on the sidewalls for isolation. The collector is formed with a P+ layer buried in the N- layer. Subsequently, the P- EPI layer is deposited and an N+ sinker is diffused down to the N+ buried layer to complete the isolation. The emitter of the vertical PNP transistor is formed during the same step as the P+ source/drain implant for the CMOS transistors. By forming the collector and its isolation regions in the substrate before depositing the EPI layer, the process is compatible with forming EEPROM which is done after the epi is deposited. An earlier implantation of the N base layer in the front-end of the process allows a deeper base junction depth, for formation of a high voltage PNP transistor.