Alon A Kfir

US Patent:

7379861, May 27, 2008

Filed:

May 19, 2005

Appl. No.:

11/133819

Inventors:

Alon Kfir - San Jose CA, US
Viktor Salitrennik - San Jose CA, US

Assignee:

Quickturn Design Systems, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

703 28, 703 15, 703 24, 703 27, 703 22, 714725, 717128

Abstract:

An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circuits that can be based on any signal generated by the device under test during run time, including signals that were optimized out of the design during the compilation process. The dynamic netlists can be loaded and used in the emulator without having to recompile the entire design, which could take many hours. This enables a user to quickly and efficiently debug circuit designs.

US Patent:

7440884, Oct 21, 2008

Filed:

Feb 24, 2003

Appl. No.:

10/373558

Inventors:

Platon Beletsky - Sunnyvale CA, US
Alon Kfir - San Jose CA, US

Assignee:

Quickturn Design Systems, Inc. - San Jose CA

International Classification:

G06F 9/455

US Classification:

703 24, 703 14

Abstract:

A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

US Patent:

7555424, Jun 30, 2009

Filed:

Mar 16, 2006

Appl. No.:

11/377762

Inventors:

Alon Kfir - San Jose CA, US
Platon Beletsky - San Jose CA, US

Assignee:

Quickturn Design Systems, Inc. - San Jose CA

International Classification:

G06F 9/455
G06F 11/16

US Classification:

703 24, 703 27, 710 8, 711 6

Abstract:

Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

US Patent:

20020162084, Oct 31, 2002

Filed:

Nov 19, 2001

Appl. No.:

09/989774

Inventors:

Michael Butts - Portland OR, US
Ming Wang - Lafayette CA, US
Alon Kfir - San Jose CA, US

International Classification:

G06F017/50

US Classification:

716/017000

Abstract:

A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

US Patent:

20030154458, Aug 14, 2003

Filed:

Jan 30, 2003

Appl. No.:

10/356919

Inventors:

Michael Butts - Portland OR, US
Ming Wang - Lafayette CA, US
Alon Kfir - San Jose CA, US

Assignee:

Quickturn Design Systems, Inc.

International Classification:

G06F017/50

US Classification:

716/017000

Abstract:

A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.