Brian Andrew Winstead

US Patent:

7414877, Aug 19, 2008

Filed:

Jan 23, 2006

Appl. No.:

11/337355

Inventors:

James D. Burnett - Austin TX, US
Brian A. Winstead - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/00

US Classification:

365154, 365 63, 365156

Abstract:

An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22. 5. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.

US Patent:

7420202, Sep 2, 2008

Filed:

Nov 8, 2005

Appl. No.:

11/269303

Inventors:

Vance H. Adams - Austin TX, US
Paul A. Grudowski - Austin TX, US
Venkat R. Kolagunta - Austin TX, US
Brian A. Winstead - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/06
H01L 21/31

US Classification:

257 18, 257 20, 257190, 257505, 257506, 257507, 257509, 257524, 438151, 438196, 438404, 438405, 438595, 438764, 438765, 438769, 438770, 438775, 438778, 438787, 438791, 372 45011

Abstract:

An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

US Patent:

7435639, Oct 14, 2008

Filed:

May 31, 2006

Appl. No.:

11/443627

Inventors:

Brian A. Winstead - Austin TX, US
Omar Zia - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Marius K. Orlowski - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438199, 438311, 257E21632

Abstract:

A semiconductor process and apparatus provide a planarized hybrid substrate () by exposing a buried oxide layer () in a first area (), selectively etching the buried oxide layer () to expose a first semiconductor layer () in a second smaller seed area (), and then epitaxially growing a first epitaxial semiconductor material from the seed area () of the first semiconductor layer () that fills the second trench opening () and grows laterally over the exposed insulator layer () to fill at least part of the first trench opening (), thereby forming a first epitaxial semiconductor layer () that is electrically isolated from the second semiconductor layer (). By forming a first SOI transistor device () over a first SOI layer () using deposited (100) silicon and forming first SOI transistor () over an epitaxially grown (110) silicon layer (), a high performance CMOS device is obtained.

US Patent:

7468313, Dec 23, 2008

Filed:

May 30, 2006

Appl. No.:

11/420849

Inventors:

Victor H. Vartanian - Dripping Springs TX, US
Brian A. Winstead - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/04

US Classification:

438511, 438510, 257E21634

Abstract:

A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors are fabricated in the first region and the second region respectively. Third and possibly fourth regions of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region. The fourth active layer region may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.

US Patent:

7479422, Jan 20, 2009

Filed:

Mar 10, 2006

Appl. No.:

11/373536

Inventors:

Brian A. Winstead - Austin TX, US
Ted R. White - Austin TX, US
Da Zhang - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438197, 438222, 438299, 257E21431, 257E21633, 257E21634

Abstract:

A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.

US Patent:

7488635, Feb 10, 2009

Filed:

Oct 26, 2005

Appl. No.:

11/260849

Inventors:

Brian A. Winstead - Austin TX, US
James D. Burnett - Austin TX, US
Sinan Goktepeli - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438199, 438217, 438229, 438527, 438528

Abstract:

A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.

US Patent:

7572706, Aug 11, 2009

Filed:

Feb 28, 2007

Appl. No.:

11/680181

Inventors:

Da Zhang - Austin TX, US
Brian A. Winstead - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336
H01L 21/8236

US Classification:

438302, 438274, 438300, 438301, 438303, 438305, 257E21177, 257E2129

Abstract:

A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.

US Patent:

7608898, Oct 27, 2009

Filed:

Oct 31, 2006

Appl. No.:

11/554851

Inventors:

James D. Burnett - Meylan, FR
Brian A. Winstead - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 29/78
H01L 21/8242

US Classification:

257384, 257296, 257E29271

Abstract:

A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.