Charles H Winstead

Address:

3933 NW Devoto Ln, Portland, OR 97229

Phone:

5035300555

VIN:

WDDHF8HB1BA319562

Make:

MERCEDES-BENZ

Model:

E-CLASS

Year:

2011

US Patent:

7062410, Jun 13, 2006

Filed:

Jun 23, 2004

Appl. No.:

10/874395

Inventors:

Charles H. Winstead - Portland OR, US
Yiqing Zhou - Portland OR, US
Carrie Auyeung - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/30
G06F 17/50

US Classification:

702183, 716 4

Abstract:

A system for conducting transistor performance analysis is disclosed, in which automatic graph plotting is interactively enhanced with human judgment. The system includes executing transistor performance analysis software, which receives templates specifying parameters, graph charting options, and algorithms, as well as a database of transistor values, as its inputs. The software produces an output document with linked graphs and a summary report. The software extracts, filters and applies statistical regression to large quantities of data. The software also applies statistical filtering to the data and automatically plots hundreds of charts and graphs based on the data. Graphs are color-coded to highlight relationships that suffer from unusually high noise in the data. Users can manually adjust lines on the graphs, which are automatically reflected in dependent graphs and the summary report. Changes to program methodology can be achieved by changing the template rather than by modifying the software.

US Patent:

7483760, Jan 27, 2009

Filed:

Dec 20, 2005

Appl. No.:

11/312131

Inventors:

Jiang Qu - Portland OR, US
Ercan U. Acar - Portland OR, US
Charles H. Winstead - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

700 97, 700100, 700103, 700105, 707100

Abstract:

In one embodiment, a method for upfront specification of lot process parameters to enable automated processing is disclosed. The method comprises building a hierarchical representation of a process plan for a manufacturing object using data structures to represent operational flows of the manufacturing object, performing a query execution on the hierarchical representation to determine one or more of the data structures affected by a global flow change (GFC), and implementing a locking protocol to preserve data integrity in the one or more data structures affected by the GFC. Other embodiments are also described.

US Patent:

7571019, Aug 4, 2009

Filed:

Dec 30, 2005

Appl. No.:

11/325926

Inventors:

Charles H. Winstead - Portland OR, US
Rajshree P. Sankaran - Portland OR, US
Samer M. Taha - Beaverton OR, US
Jiang Qu - Portland OR, US
Chandra Mouli - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 19/00

US Classification:

700100, 700 86, 700 97, 700121

Abstract:

According to embodiments of the invention, an integrated configuration, flow and execution systems (ICFES) may be used to specify, control and record a history of processing of both semiconductor device experimental lots and production lots of wafers. Moreover, the system allows combining of one or more partial flows of pre-existing flow blocks, and special processing into another processing flow block. A lot plan can be created that includes the flow block, and the lot plan can be updated to include partial flows and special processing before or during processing of the lot plan.

US Patent:

20050273685, Dec 8, 2005

Filed:

Jun 8, 2004

Appl. No.:

10/863084

Inventors:

Sanjay Sachdev - Hillsboro OR, US
Charles Winstead - Portland OR, US

International Classification:

G01R031/28
G06F011/00

US Classification:

714742000

Abstract:

Automating techniques provide a way to create efficient test programs for characterizing semiconductor devices, such as those on a silicon die sample. Typically, test program creation is a drawn out process involving data entry for every test to be run as part of the test program. The described techniques improve test algorithm selection and automatically populate the test algorithm data in creating the test program. The automatic population may occur by accessing test structure, header, and test algorithm catalogs. The test structure catalog contains physical data for the test program, while the header catalog contains global parameter values. The test algorithm catalog has all of the various test algorithms that may be run in a given test, where these test algorithms may be in a template form and specific to any number of different test language abstractions. After test program creation, a validation process is executed to determine if the test program data is valid. Invalid data may be flagged, in an example. Once validated, techniques are described for converting the validated test program into an executable form, by formatting the various test algorithm data in the test program into a form compatible with the applicable test language abstraction selected by the user or the tester.

US Patent:

20070233297, Oct 4, 2007

Filed:

Mar 30, 2006

Appl. No.:

11/394016

Inventors:

Charles Winstead - Portland OR, US
Daymion Reynolds - Mesa AZ, US
Yashmeet Khopkar - Phoenix AZ, US

International Classification:

G06F 17/50
G06F 19/00

US Classification:

700096000, 703014000

Abstract:

A manufacturing execution system may be simulated, for example, for volume testing. In a semiconductor fabrication embodiment, a volume capability, such as a number of wafer starts, may be determined for a given version of a manufacturing execution system. In some cases, the simulation runs operations or scripts under more realistic conditions. A check can determine whether an appropriate condition exists at an appropriate lot or tool and the desired operation may then be run from that lot or tool from an appropriate state.

US Patent:

20080081438, Apr 3, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/541230

Inventors:

Mandar Chincholkar - Beaverton OR, US
Michael J. Scott - Gilbert AZ, US
Charles H. Winstead - Portland OR, US
Rajshree Sankaran - Portland OR, US

International Classification:

H01L 21/00

US Classification:

438464

Abstract:

Embodiments of logical groups of wafers in semiconductor processing are presented herein.

US Patent:

20160314290, Oct 27, 2016

Filed:

Dec 23, 2013

Appl. No.:

14/368344

Inventors:

- Santa Clara CA, US
Tobias M. KOHLENBERG - Portland OR, US
Mark PRICE - Placitas NM, US
Min LIU - Portland OR, US
Charles H. WINSTEAD - Portland OR, US
Matthew ROYER - Hillsboro OR, US

International Classification:

G06F 21/32
G06K 9/00

Abstract:

Technologies for authenticating a user to a computing device include determining a hair follicle pattern of a portion of the user's skin and comparing the determined hair follicle pattern to an authenticated hair follicle pattern to authenticate the user. The hair follicle pattern of the portion of the user's skin may, be generated by a camera of the computing device, and the authenticated hair follicle pattern may be stored in a secure storage of the computing device. Features of the computing device may be enabled based on the particular authenticated hair follicle pattern to which the determined hair follicle matches. Additionally, in some embodiments, one or more additional biometric authentications may be used, and the user may be authenticated based on the particular combination of the authenticated hair follicle pattern and the additional biometric authentication(s).

US Patent:

20160078350, Mar 17, 2016

Filed:

Sep 17, 2014

Appl. No.:

14/488809

Inventors:

Mark D. Yarvis - Portland OR, US
Mark MacDonald - Beaverton OR, US
Charles H. Winstead - Portland OR, US
Wah Yiu Kwong - Beaverton OR, US
Daniel S. Willis - Portland OR, US

International Classification:

G06N 5/04

Abstract:

Technologies for contextual platform recommendations including a computing device with a number of platform capabilities, including any combination of hardware capabilities and software capabilities. The computing device stores context data based on the current context of the computing device and determines a user profile based on the context data. The user profile is indicative of typical behavior of the user of the computing device. The computing device determines a recommended platform capability from a number of available platform capabilities based on the user profile. The computing device notifies the user of the recommended platform capability. The computing device may also provide the notification only when the recommended platform capability is relevant to the current device context. The computing device may transmit the user profile to a recommendation service, which may generate additional recommendations for platform capabilities. Other embodiments are described and claimed.