Gang Xue Z Zhang

US Patent:

7139987, Nov 21, 2006

Filed:

Jul 11, 2003

Appl. No.:

10/618237

Inventors:

Gang Zhang - Pittsburgh PA, US
Enis Aykut Dengi - Tempe AZ, US
Ronald A. Rohrer - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 8, 716 9

Abstract:

In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.

US Patent:

7583152, Sep 1, 2009

Filed:

Jan 4, 2008

Appl. No.:

11/969364

Inventors:

Gang Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03L 1/02
H03L 7/085
H03L 7/089
H03L 7/18
H04B 1/40

US Classification:

331 25, 331 1 A, 331 16, 331 17, 331176, 455 76, 455260

Abstract:

A phase-locked loop includes a phase-to-digital converter portion as well as a novel correction portion. The phase-to-digital converter (PDC) portion outputs a stream of first phase error words. The novel correction portion receives the first phase error words and generates a stream of second phase error words that is supplied to a loop filter. The PDC portion has a phase-to-digital transfer function that exhibits certain imperfections. In a first example, the correction portion determines an average difference between pairs of first phase error words, and uses this average difference to normalize the first phase error words to correct for changes in PDC portion transfer function slope due to changes in delay element propagation delay. In a second example, the correction portion corrects for gain mismatches in PDC portion transfer function. In a third example, the correction portion corrects for offset mismatches in PDC portion transfer function.

US Patent:

7735048, Jun 8, 2010

Filed:

Nov 24, 2004

Appl. No.:

10/997639

Inventors:

Gang Zhang - Pittsburgh PA, US
Enis Aykut Dengi - Tempe AZ, US
Ronald A. Rohrer - Saratoga CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 703 2

Abstract:

Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit resizing to enable parasitic robust designs. The worst-case parasitic corners are generated efficiently without expensive statistical computations. A performance-driven placement with simultaneous fast rough routing and device tuning generates high quality placements and compensates for layout induced performance degradations. A regression-tree based macromodeling methodology is introduced for modeling of electrical performances to enable true performance-driven layout synthesis. To improve sampling quality, an annealing-based placer can be used to perform sampling. The modeling methodology can be adapted to include automatically adjusting the device tuning ranges to meet certain model accuracy requirements.

US Patent:

7759993, Jul 20, 2010

Filed:

Aug 6, 2008

Appl. No.:

12/187321

Inventors:

Gang Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03L 7/06

US Classification:

327159, 327150

Abstract:

Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by-N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigma-to-delta modulator are disclosed.

US Patent:

7864915, Jan 4, 2011

Filed:

Oct 8, 2008

Appl. No.:

12/247970

Inventors:

Gang Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03K 23/50

US Classification:

377119, 377 37

Abstract:

Design techniques for a low-power asynchronous counter. In an exemplary embodiment, the clock inputs and signal outputs of a plurality of flip-flops are serially concatenated to implement an asynchronous counting mechanism. The signal outputs of the plurality of flip-flops are sampled by successively delayed versions of a reference signal. Further design techniques for generating successively delayed versions of the reference signal are disclosed. In an exemplary embodiment, the asynchronous counting techniques may be utilized in a high-speed counter for a digital-phase locked loop (DPLL).

US Patent:

7876871, Jan 25, 2011

Filed:

Nov 30, 2006

Appl. No.:

11/565062

Inventors:

Gang Zhang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03D 3/24

US Classification:

375374, 375327, 375373, 375375, 375376

Abstract:

Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and second signals based on only the first signal. The first and second signals may be up and down signals, respectively, or may be down and up signals, respectively. The phase frequency detector may delay the first signal by a predetermined amount, generate a reset signal based on the delayed first signal and the second signal, and reset the first and second signals with the reset signal. The charge pump receives the first and second signals and generates an output signal indicative of phase error between the reference and clock signals.

US Patent:

7911247, Mar 22, 2011

Filed:

Feb 26, 2008

Appl. No.:

12/037503

Inventors:

Yang Xu - Chicago IL, US
Gang Zhang - San Diego CA, US
Prasad S. Gudem - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03L 7/06

US Classification:

327156

Abstract:

The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

US Patent:

8022849, Sep 20, 2011

Filed:

Apr 14, 2008

Appl. No.:

12/102768

Inventors:

Gang Zhang - San Diego CA, US
Abhishek Jajoo - Pittsburgh PA, US
Yiping Han - La Jolla CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03M 1/00

US Classification:

341142, 341155

Abstract:

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.