Joseph M Lukaitis

US Patent:

6521493, Feb 18, 2003

Filed:

May 19, 2000

Appl. No.:

09/574891

Inventors:

Johann Alsmeier - Wappingers Falls NY
Giuseppe LaRosa - Fishkill NY
Joseph Lukaitis - Pleasant Valley NY
Rajesh Rengarajan - Dresden, DE

Assignee:

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

International Classification:

H01L 218238

US Classification:

438199, 438200, 438208, 438222, 438227

Abstract:

A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

US Patent:

6958621, Oct 25, 2005

Filed:

Dec 2, 2003

Appl. No.:

10/725984

Inventors:

Giuseppe La Rosa - Fishkill NY, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Anastasios A. Katsetos - Poughkeepsie NY, US
Ping-Chuan Wang - Hopewell Jct NY, US
Stephen P. Boffoli - Wappingers Falls NY, US
Fernando J. Guarin - Millbrook NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K019/003

US Classification:

326 9, 326 82

Abstract:

A recovery circuit and a method for employing the same are provided. The recovery circuit has a current driver and, preferably two pass-gates, a first pass-gate connected in series to the current driver and a second pass-gate connected to a ground. The recovery circuit also has a recovery assembly or element and one or more contacts operatively connecting the recovery circuit to a wearout sensitive circuit or circuit element.

US Patent:

8003474, Aug 23, 2011

Filed:

Aug 15, 2008

Appl. No.:

12/192387

Inventors:

Kaushik Chanda - Fishkill NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/33

US Classification:

438333, 438132, 438215, 257529, 257E23149, 257E21592

Abstract:

An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

US Patent:

8053870, Nov 8, 2011

Filed:

Dec 15, 2009

Appl. No.:

12/638004

Inventors:

Brent A. Anderson - Jericho VT, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Jed H. Rankin - South Burlington VT, US
Robert R. Robison - Colchester VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/58

US Classification:

257637, 257635

Abstract:

Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation.

US Patent:

8298904, Oct 30, 2012

Filed:

Jan 18, 2011

Appl. No.:

13/008465

Inventors:

Joseph M. Lukaitis - Pleasant Valley NY, US
Jed H. Rankin - Richmond VT, US
Robert R. Robison - Colchester VT, US
Dustin K. Slisher - Wappingers Falls NY, US
Timothy D. Sullivan - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438384, 438385, 257E21004

Abstract:

A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

US Patent:

8378447, Feb 19, 2013

Filed:

Apr 13, 2011

Appl. No.:

13/085632

Inventors:

Kaushik Chanda - Fishkill NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257529, 257528, 257530, 257735, 257755, 257E21592, 257E23149

Abstract:

An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

US Patent:

8486796, Jul 16, 2013

Filed:

Nov 19, 2010

Appl. No.:

12/950635

Inventors:

David L. Harmon - Essex VT, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Robert R. Robison - Colchester VT, US
Dustin K. Slisher - Wappingers Falls NY, US
Jeffrey H. Sloan - Chittenden VT, US
Timothy D. Sullivan - Franklin Lakes NJ, US
Kimball M. Watson - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8222
H01L 23/62

US Classification:

438330, 438382, 257359, 257380, 257E27113, 257E27114

Abstract:

A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.

US Patent:

8530319, Sep 10, 2013

Filed:

Oct 14, 2010

Appl. No.:

12/904435

Inventors:

Ephrem G. Gebreselasie - South Burlington VT, US
Joseph M. Lukaitis - Pleasant Valley NY, US
Robert R. Robison - Colchester VT, US
William R. Tonti - Essex Junction VT, US
Ping-Chuan Wang - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20
H01L 21/44

US Classification:

438379, 438600, 438601

Abstract:

An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.