Karen C Lo

US Patent:

6744834, Jun 1, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/561142

Inventors:

Karen Lo - Saratoga CA

Assignee:

Hewlett-Packard Company - Houston TX

International Classification:

H04L 700

US Classification:

375354

Abstract:

A method and apparatus for initializing a synchronizer is provided. The initialization circuitry includes a pattern generator for generating an initialization pattern, a pattern detector for recognizing the initialization pattern, and a read select circuit. After recognition of an initialization pattern, the write pointer is set to a predetermined location in the data buffer of the synchronizer to be read. A predetermined number of cycles after receipt of a unique clock cycle identifier signal (the global frame clock) by the read select circuit, valid data in lockstep with other bitsliced interfaces can be read from the synchronizer.

US Patent:

6757347, Jun 29, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/560214

Inventors:

Karen Lo - Sunnyvale CA
Jeffery A. Benis - San Jose CA
Alan R. Desroches - San Jose CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 700

US Classification:

375355, 713401

Abstract:

Methods and apparatus for halting the data strobes transmitted over a source synchronous link to enable the data stored in the data capture flip-flops in a source synchronous receiver to be scanned out for subsequent analysis. This allows for the evaluation of the captured data without placing additional components in the functional data path and, therefore, without increasing the latency of the transmission. To provide optimal timing margins the data and data strobe paths are logically and electrically matched. This includes routing the data and data strobe signals in close proximity from the transmitter to the receiver, and through the same logical and physical elements in the transmitter and receiver. This insures that any injected link noise is experienced common-mode. In addition, the data strobe signal is preferably driven at one-half of the period of the data signal so that the data strobe and data signals experience logical state transitions at the same time and at the same frequency.

US Patent:

7068727, Jun 27, 2006

Filed:

Apr 28, 2000

Appl. No.:

09/560364

Inventors:

Karen Lo - Saratoga CA, US
Robert D. Snyder - Ouistreham, FR

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 27/04
H03K 19/00

US Classification:

375295, 365233, 326 93

Abstract:

Methods and apparatus for halting the data strobes transmitted over a source synchronous link to enable the data stored in the data capture flip-flops in a source synchronous receiver to be scanned out for subsequent analysis. This allows for the evaluation of the captured data without placing additional components in the functional data path and, therefore, without increasing the latency of the transmission. To provide optimal timing margins the data and data strobe paths are logically and electrically matched. This includes routing the data and data strobe signals in close proximity from the transmitter to the receiver, and through the same logical and physical elements in the transmitter and receiver. This insures that any injected link noise is experienced common-mode. In addition, the data strobe signal is preferably driven at one-half of the period of the data signal so that the data strobe and data signals experience logical state transitions at the same time and at the same frequency.

US Patent:

6724846, Apr 20, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/561143

Inventors:

Karen Lo - Saratoga CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 700

US Classification:

375354, 375372

Abstract:

The present invention provides a highly reliable synchronizer which provides excellent synchronization without using complicated PLL or DLL circuitry, which is simple to test, which is easily adaptable to systems which use bit-sliced data, and which does not require large chip area. The synchronizer is comprised of a first stage, a data capture circuit, preferably comprised of pair of master-slave flip-flops, that is electrically coupled to a second stage, a data selection circuit that preferably includes a FIFO comprised of N transparent latches that are electrically coupled to a multiplexer. The lack of complexity of the synchronizer design makes it smaller, faster, easier to test, and less prone to design error and manufacturing limits.