Mary E Rothwell

US Patent:

6632536, Oct 14, 2003

Filed:

Dec 28, 2000

Appl. No.:

09/752019

Inventors:

Stephen L. Buchwalter - Hopewell Junction NY
Gareth Geoffrey Hougham - Ossining NY
Kang-Wook Lee - Yorktown Heights NY
John J. Ritsko - Mount Kisko NY
Mary Elizabeth Rothwell - Ridgefield CT
Peter M. Fryer - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 904

US Classification:

428447, 428446, 428688

Abstract:

New etch barriers of indium-tin-oxide in the manufacturing process of thin film transistor-liquid crystal display are self-assembled monolayers, such as n-alkylsilanes. A typical process of applying a self-assembled monolayer is to ink a hydrolyzed n-octadecyltrimethoxysilane solution on to a stamp and then to transfer the solution onto ITO. The surface of the stamp may be polar enough to be wet with polar self-assembled monolayer solutions of an akylsilane. A non-polar stamp surface may be treated with oxygen plasma to obtain a wettable polar surface.

US Patent:

6783717, Aug 31, 2004

Filed:

Apr 22, 2002

Appl. No.:

10/127373

Inventors:

Gareth Hougham - Ossining NY
Peter Fryer - Yorktown Heights NY
Ronald Nunes - Hopewell Junction NY
Mary Beth Rothwell - Ridgefield CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B29C 3340

US Classification:

264219, 264225

Abstract:

A process of making a high precision microcontact printing stamp in which an elastomeric monomer or oligomer is introduced into a mold wherein a photoresist master imprinted with a microcircuit design in negative relief is predisposed. The monomer or oligomer is cured at a temperature no higher than about ambient temperature whereby a distortion-free microcontact printing stamp having the microcircuit design of the photoresist master in positive relief is formed.

US Patent:

6881366, Apr 19, 2005

Filed:

Apr 22, 2002

Appl. No.:

10/127375

Inventors:

Gareth Hougham - Ossining NY, US
Peter Fryer - Yorktown Heights NY, US
Ronald Nunes - Hopewell Junction NY, US
Mary Beth Rothwell - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B29C031/04
B29C039/24

US Classification:

264 85, 264102, 264319

Abstract:

A process of making a microcontact printing stamp useful in the microcontact printing of a microcircuit. In this process an elastomeric microcontact printing stamp is formed by curing a degassed liquid elastomeric monomer or oligomer, optionally saturated with helium, a mixture of helium and an inert gas or a mixture of hydrogen and an inert gas, in a mold in which a photoresist master, defining a microcircuit in negative relief, is predisposed above a backplane.

US Patent:

6890599, May 10, 2005

Filed:

Jun 13, 2003

Appl. No.:

10/461215

Inventors:

Stephen L. Buchwalter - Hopewell Junction NY, US
Gareth Geoffrey Hougham - Ossining NY, US
Kang-Wook Lee - Yorktown Heights NY, US
John J. Ritsko - Mount Kisko NY, US
Mary Elizabeth Rothwell - Ridgefield CT, US
Peter M. Fryer - Yorktown Heights NY, US

Assignee:

Intellectual Business Machines Corporation - Armonk NY

International Classification:

B05D001/32
B05D003/00
B05D005/00

US Classification:

427272, 427156, 427259, 427271, 427275, 427282

Abstract:

New etch barriers of indium-tin-oxide in the manufacturing process of thin film transistor-liquid crystal display are self-assembled monolayers, such as n-alkylsilanes. A typical process of applying a self-assembled monolayer is to ink a hydrolyzed n-octadecyltrimethoxysilane solution on to a stamp and then to transfer the solution onto ITO. The surface of the stamp may be polar enough to be wet with polar self-assembled monolayer solutions of an akylsilane. A non-polar stamp surface may be treated with oxygen plasma to obtain a wettable polar surface.

US Patent:

7566632, Jul 28, 2009

Filed:

Feb 6, 2008

Appl. No.:

12/026843

Inventors:

Mary B. Rothwell - Ridgefield CT, US
Ghavam G. Shahidi - Yorktown Heights NY, US
Roy R. Yu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H21L 21/50

US Classification:

438455, 438106, 438107, 257E23001, 257E23003, 257731

Abstract:

A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).

US Patent:

7608538, Oct 27, 2009

Filed:

Jan 5, 2007

Appl. No.:

11/620497

Inventors:

Hariklia Deligianni - Tenafly NJ, US
Qiang Huang - Ossining NY, US
John P. Hummel - Millbrook NY, US
Lubomyr T. Romankiw - Briarcliff Manor NY, US
Mary B. Rothwell - Ridgefield CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438675, 257625, 257E21175, 205 67, 205 87, 205 93, 205925, 205 74, 205 69, 205127, 427162, 204194

Abstract:

The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.

US Patent:

7695897, Apr 13, 2010

Filed:

May 8, 2006

Appl. No.:

11/429709

Inventors:

James J. Bucchignano - Yorktown Heights NY, US
Gerald W. Gibson - Danbury CT, US
Mary B. Rothwell - Ridgefield CT, US
Roy R. Yu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03F 7/00
G03F 7/26

US Classification:

430313, 430323, 430317, 430316, 430296, 216 72, 216 58

Abstract:

The present invention relates to improved methods and structures for forming interconnect patterns in low-k or ultra low-k (i. e. , having a dielectric constant ranging from about 1. 5 to about 3. 5) interlevel dielectric (ILD) materials. Specifically, reduced lithographic critical dimensions (CDs) (i. e. , in comparison with target CDs) are initially used for forming a patterned resist layer with an increased thickness, which in turn allows use of a simple hard mask stack comprising a lower nitride mask layer and an upper oxide mask layer for subsequent pattern transfer. The hard mask stack is next patterned by a first reactive ion etching (RIE) process using an oxygen-containing chemistry to form hard mask openings with restored CDs that are substantially the same as the target CDs. The ILD materials are then patterned by a second RIE process using a nitrogen-containing chemistry to form the interconnect pattern with the target CDs.

US Patent:

7855455, Dec 21, 2010

Filed:

Sep 26, 2008

Appl. No.:

12/239688

Inventors:

Sampath Purushothaman - Yorktown Heights NY, US
Mary E. Rothwell - Ridgefield CT, US
Ghavam Ghavami Shahidi - Pound Ridge NY, US
Roy Rongqing Yu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/48

US Classification:

257750, 257758, 257760, 257E2301, 257E23011

Abstract:

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.