Richard F Avra

US Patent:

8078800, Dec 13, 2011

Filed:

Jun 5, 2009

Appl. No.:

12/479063

Inventors:

Maziar H. Moallem - Cupertino CA, US
Sanjay Mansingh - Santa Clara CA, US
Richard F. Avra - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00

US Classification:

711118

Abstract:

In one embodiment, an integrated circuit includes a processor, an internal memory, and a memory controller coupled to an external memory. The integrated circuit may support two or more modes of operation, with different operating points. To switch from one operating point to another, code executed by the processor may copy switch code from the external memory into the internal memory, and may jump to the switch code. Executing out of the internal memory, the switch code may communicate with the memory controller to cause the external memory to enter into self-refresh mode. The operating point may be altered, and the switch code may reinitialize the memory controller after the integrated circuit has stabilized at the new operating point. After the memory controller's physical interface circuit has relocked, the external memory may exit self-refresh mode.

US Patent:

8250250, Aug 21, 2012

Filed:

Oct 28, 2009

Appl. No.:

12/607201

Inventors:

Maziar H. Moallem - Cupertino CA, US
Richard F. Avra - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 3/00

US Classification:

710 20, 710 22, 710 23, 714 1, 714 511

Abstract:

In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.

US Patent:

8479135, Jul 2, 2013

Filed:

Dec 15, 2009

Appl. No.:

12/638178

Inventors:

Juhong Zhu - Sunnyvale CA, US
Gaurav S. Gulati - Cupertino CA, US
Maziar H. Moallem - Cupertino CA, US
Greg H. Nayman - Mountain View CA, US
Richard F. Avra - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 17/50

US Classification:

716117, 716116

Abstract:

In an embodiment, a methodology for automating the generation of a programmable logic device implementation of at least a portion of an integrated circuit is contemplated. The methodology may operate on one or more hardware description language (HDL) files which describe the integrated circuit as an input. Additionally, one or more user-generated control files may be input to the methodology. The methodology may process the one or more HDL files, generating a bitstream to program one or more programmable logic devices to implement the described design. The methodology may include automated modification of the HDL files to prepare them for programmable logic device implementation, automated pad ring generation, automated pin multiplexing, daughter card definition, partitioning, etc.

US Patent:

20120290881, Nov 15, 2012

Filed:

Jul 19, 2012

Appl. No.:

13/553301

Inventors:

Maziar H. Moallem - Cupertino CA, US
Richard F. Avra - Los Altos CA, US

International Classification:

G06F 11/28

US Classification:

714 37, 714E11178

Abstract:

In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.

US Patent:

55197159, May 21, 1996

Filed:

Jan 27, 1995

Appl. No.:

8/379770

Inventors:

Hong Hao - Sunnyvale CA
Richard F. Avra - Los Altos CA
James C. Hunt - Redwood City CA
Kanti Bhabuthmal - Fremont CA

Assignee:

Sun Microsystems, Inc.

International Classification:

H04B 1700

US Classification:

371 223

Abstract:

A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially, the microprocessor's internal clock is disabled. Then for each memory location specified in the compiled program, the memory content associated with that location is loaded into the appropriate microprocessor cache. This is accomplished in two primary steps. First, the memory content is shifted into positions on the pins of the microprocessor by a boundary scan shift operation via an IEEE 1149. 1 interface. Second, after the pins have the appropriate bit values for the current memory content, an external clock supplies the microprocessor with clock cycles that are then used by the microprocessor to control the loading of data/instructions from the pins into the appropriate data or instruction cache. The process of loading the pins with data via boundary scan, and then shifting the data into appropriate caches is repeated for each memory content of the compiled program until all instructions in the program have been loaded into the appropriate caches. Thereafter, the microprocessor is forced into normal execution mode by resetting the microprocessor to reenable its internal clock.