Sean H Kao

US Patent:

7368946, May 6, 2008

Filed:

Jun 16, 2006

Appl. No.:

11/454315

Inventors:

Arifur Rahman - San Jose CA, US
Sean W. Kao - South Pasadena CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19/173
G06F 7/38

US Classification:

326 46, 326 38

Abstract:

The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices having low and high voltage domains. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for controlling the propagation of a selected input signal through the pass gates of the multiplexer circuit. For some embodiments, some of the select signals may be decoded to generate a number of decoded select signals that can be used to control the selective routing of signals through the multiplexer.

US Patent:

7417454, Aug 26, 2008

Filed:

Aug 24, 2005

Appl. No.:

11/210498

Inventors:

Arifur Rahman - San Jose CA, US
Tim Tuan - San Jose CA, US
Sean W. Kao - Campbell CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 41, 326 47, 326113

Abstract:

An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

US Patent:

7463056, Dec 9, 2008

Filed:

Dec 12, 2005

Appl. No.:

11/301056

Inventors:

James B. Anderson - Santa Cruz CA, US
Sean W. Kao - Campbell CA, US
Arifur Rahman - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

An FPGA system includes a combined shift register and look up table (LUT) forming a shift register LUT (SRL) that provides data write, reset and shift enable on a cell-by-cell basis. The data write and reset can be performed during FPGA operation without requiring a number of frames or columns of configuration memory cells to be reprogrammed, as with conventional SRAM cells. The shift enable provides for synchronization to facilitate the cell-by-cell write and reset.

US Patent:

7477072, Jan 13, 2009

Filed:

Jan 17, 2006

Appl. No.:

11/333972

Inventors:

Sean Kao - Campbell CA, US
Arifur Rahman - San Jose CA, US
James Anderson - Santa Cruz CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H01L 25/00
H03K 19/177

US Classification:

326 41, 326 40

Abstract:

A circuit for enabling partial reconfiguration of memory elements of a device having programmable logic is described. The circuit comprises a block of memory cells comprising a look-up table of a configurable logic block; and a reset signal coupled to the block of memory elements, the reset signal enabling partial reconfiguration of the memory cells of the configurable logic block. Each the memory cell may be coupled to receive the reset signal enabling the partial reconfiguration of the block of memory cells of the configurable logic block. The reset signal may comprise a plurality of signals, wherein each signal of the plurality of signals is coupled to a memory cell of the block of memory cells. Each memory cell may also receive a signal for setting an initial state. A method of enabling partial reconfiguration of memory cells of a look-up table of a programmable logic device is also described.

US Patent:

7477073, Jan 13, 2009

Filed:

Jun 16, 2006

Appl. No.:

11/454316

Inventors:

Tim Tuan - San Jose CA, US
Arifur Rahman - San Jose CA, US
Satyaki Das - Los Gatos CA, US
Sean W. Kao - South Pasadena CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19/177
H03K 19/0175

US Classification:

326 41, 326101, 326 63

Abstract:

A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

US Patent:

7490302, Feb 10, 2009

Filed:

Aug 3, 2005

Appl. No.:

11/196179

Inventors:

Arifur Rahman - San Jose CA, US
Sean W. Kao - Campbell CA, US
Tim Tuan - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 16, 716 18

Abstract:

Power-gating circuit resources of an integrated circuit is described. The circuit resources are associated into sets responsive to utilization levels. The associating includes providing a first set of the sets, a first number of the circuit resources in the first set being associated with a first level of utilization. The associating also includes providing a second set of the sets, a second number of the circuit resources in the second set being associated with a second level of utilization. The first number is less than the second number responsive to the first level of utilization being greater than the second level of utilization. The circuit resources of the first set are commonly coupled to a reference voltage level via a first gating circuit. The circuit resources of the second set are commonly gated to the same or a different reference voltage level via a second gating circuit.

US Patent:

7498835, Mar 3, 2009

Filed:

Nov 4, 2005

Appl. No.:

11/268265

Inventors:

Arifur Rahman - San Jose CA, US
Sean W. Kao - Campbell CA, US
Tim Tuan - San Jose CA, US
Patrick J. Crotty - San Jose CA, US
Jinsong Oliver Huang - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/173
G11C 5/14

US Classification:

326 38, 326 39, 326 46, 365226, 365227, 365229

Abstract:

A PLD () includes a power management unit (PMU ) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits () that power CLBs (), IOBs (), and configuration memory cells (), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.

US Patent:

7500060, Mar 3, 2009

Filed:

Mar 16, 2007

Appl. No.:

11/724808

Inventors:

James B. Anderson - Santa Cruz CA, US
Sean W. Kao - Pasadena CA, US
Arifur Rahman - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711132, 711203, 711 6, 711170

Abstract:

A hardware stack (HSTACK) structure using programmable logic can include a look-up table (LUT) random access memory (RAM) circuit and circuitry within the LUT RAM circuit for propagating data upwards and downwards. The hardware structure can be arbitrarily assembled into a larger structure by adding stacks to a top portion, a bottom portion, or a portion between the top portion and the bottom portion. The hardware stack structure can further include a virtual stack (VSTACK) structure coupled to the HSTACK structure within a field programmable gate array (FPGA) fabric. The VSTACK can be arranged in the form of an appended peripheral memory and cache control for virtual extension to an HSTACK address space. The hardware stack structure can further include an auxiliary reset circuit.