Susan Y Kao

US Patent:

20030003403, Jan 2, 2003

Filed:

Sep 7, 2001

Appl. No.:

09/948719

Inventors:

Everett Lee - Los Altos CA, US
Susan Kao - Los Altos CA, US

International Classification:

G03F007/40

US Classification:

430/313000, 430/322000, 430/330000

Abstract:

A method and articles of manufacture created from this method wherein a portion of a layer of photoresist material are irradiated to cause the creation of a chemical within that portion, and then the passage of time and/or the application of heat is used to cause the chemical to propagate to another portion of the layer of photoresist material.

US Patent:

20030003408, Jan 2, 2003

Filed:

Jun 29, 2001

Appl. No.:

09/895352

Inventors:

Everett Lee - Los Altos CA, US
Susan Kao - Los Altos CA, US

International Classification:

G03F007/40

US Classification:

430/330000, 430/313000, 430/322000

Abstract:

A method and articles of manufacture created from this method wherein a portion of a layer of photoresist material are irradiated to cause the creation of a chemical within that portion, and then the passage of time and/or the application of heat is used to cause the chemical to propagate to another portion of the layer of photoresist material.

US Patent:

52293114, Jul 20, 1993

Filed:

Mar 25, 1992

Appl. No.:

7/859264

Inventors:

Stefan K. Lai - Belmont CA
Daniel N. Tang - San Jose CA
Simon Y. Wang - Sunnyvale CA
Susan L. Kao - Los Altos CA
Baylor B. Triplett - La Honda CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2170

US Classification:

437 43

Abstract:

A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed. The method of the present invention includes covering the active regions of the semiconductor device with a protective titanium barrier layer which is deposited directly underneath the ordinary metalization layers used for connecting the devices to bit and word lines within an array. Inclusion of the titanium barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices.