Shu-Ling W Garver

US Patent:

7568115, Jul 28, 2009

Filed:

Sep 28, 2005

Appl. No.:

11/238489

Inventors:

Shekhar Borkar - Beaverton OR, US
Tanay Karnik - Portland OR, US
Shu-ling Garver - Scappoose OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/26

US Classification:

713300, 713320

Abstract:

According to embodiments of the disclosed subject matter in this application, a power management system with multiple voltage regulator (“VRs”) may be used to supply power to cores in a many-core processor. Each VR may supply power to a core or a part of a core. Different VRs may provide multiple voltages to a core/part in the many-core processor. The value of the output voltage of a VR may be modulated under the direction of the core/part to which the voltage regulator supplies power. In one embodiment, the multiple VRs may be integrated with cores in a single die. In another embodiment, the power management system with multiple VRs may be on a die (“the VR die”) separate from the die of the many-core processor. The VR die may be included in the same package as the many-core processor die.

US Patent:

7774590, Aug 10, 2010

Filed:

Mar 23, 2006

Appl. No.:

11/387385

Inventors:

Shekhar Borkar - Beaverton OR, US
Yatin Hoskote - Portland OR, US
Shu-Ling Garver - Scappoose OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/177

US Classification:

713100, 713 1

Abstract:

In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.

US Patent:

20070074011, Mar 29, 2007

Filed:

Sep 28, 2005

Appl. No.:

11/238488

Inventors:

Shekhar Borkar - Beaverton OR, US
Yatin Hoskote - Portland OR, US
Shu-Ling Garver - Scappoose OR, US

International Classification:

G06F 15/00

US Classification:

712227000

Abstract:

According to embodiments of the disclosed subject matter, cores in a many-core processor may be periodically tested to obtain and/or refresh their dynamic profiles. The dynamic profile of a core may include information on its maximum operating frequency, power consumption, power leakage, functional correctness, and other parameters, as well as the trending information of these parameters. Once a dynamic profile has been created for each core, cores in a many-core processor may be grouped into different bins according to their characteristics. Based on dynamic profiles and the grouping information, the operating system (“OS”) or other software may allocate a task to those cores that are most suitable for the task. The interconnect fabric in the many-core processor may be reconfigured to ensure a high level of connectivity among the selected cores. Additionally, cores may be re-allocated and/or re-balanced to a task in response to changes in the environment.

US Patent:

20100268931, Oct 21, 2010

Filed:

Jun 28, 2010

Appl. No.:

12/824945

Inventors:

Shekhar Borkar - Beaverton OR, US
Yatin Hoskote - Portland OR, US
Shu-Ling Garver - Scappoose OR, US

International Classification:

G06F 11/28
G06F 9/00

US Classification:

713100, 714 40, 714E11178

Abstract:

In one embodiment, the present invention includes a method for performing dynamic testing of a many-core processor including a plurality of cores, manipulating data obtained from the dynamic testing into profile information of the many-core processor, and storing the profile information in a non-volatile memory. The non-volatile memory may be within the many-core processor, in some embodiments. Other embodiments are described and claimed.